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stm32 /stm32u5 /STM32U535 /GPDMA1 /SMISR

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Interpret as SMISR

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https://regviz.com/r/stm32/stm32u5/STM32U535/GPDMA1/SMISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MIS0)MIS0 0 (MIS1)MIS1 0 (MIS2)MIS2 0 (MIS3)MIS3 0 (MIS4)MIS4 0 (MIS5)MIS5 0 (MIS6)MIS6 0 (MIS7)MIS7 0 (MIS8)MIS8 0 (MIS9)MIS9 0 (MIS10)MIS10 0 (MIS11)MIS11 0 (MIS12)MIS12 0 (MIS13)MIS13 0 (MIS14)MIS14 0 (MIS15)MIS15

Description

secure masked interrupt status register

Fields

MIS0

MIS0
MIS1

MIS1
MIS2

MIS2
MIS3

MIS3
MIS4

MIS4
MIS5

MIS5
MIS6

MIS6
MIS7

MIS7
MIS8

MIS8
MIS9

MIS9
MIS10

MIS10
MIS11

MIS11
MIS12

MIS12
MIS13

MIS13
MIS14

MIS14
MIS15

MIS15

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32