Regviz

stm32 /stm32u5 /STM32U535 /GTZC1_TZIC /FCR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FCR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32u5/STM32U535/GTZC1_TZIC/FCR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CTIM1F)CTIM1F 0 (CSPI1F)CSPI1F 0 (CTIM8F)CTIM8F 0 (CUSART1F)CUSART1F 0 (CTIM15F)CTIM15F 0 (CTIM16F)CTIM16F 0 (CTIM17F)CTIM17F 0 (CSAI1F)CSAI1F

Description

TZIC flag clear register 2

Fields

CTIM1F

clear the illegal access flag for TIM1
CSPI1F

clear the illegal access flag for SPI1
CTIM8F

clear the illegal access flag for TIM8
CUSART1F

clear the illegal access flag for USART1
CTIM15F

clear the illegal access flag for TIM5
CTIM16F

clear the illegal access flag for TIM6
CTIM17F

clear the illegal access flag for TIM7
CSAI1F

clear the illegal access flag for SAI1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32