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stm32 /stm32u5 /STM32U535 /GTZC1_TZIC /IER2

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Interpret as IER2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1IE)TIM1IE 0 (SPI1IE)SPI1IE 0 (TIM8IE)TIM8IE 0 (USART1IE)USART1IE 0 (TIM15IE)TIM15IE 0 (TIM16IE)TIM16IE 0 (TIM17IE)TIM17IE 0 (SAI1IE)SAI1IE

Description

TZIC interrupt enable register 2

Fields

TIM1IE

illegal access interrupt enable for TIM1
SPI1IE

illegal access interrupt enable for SPI1
TIM8IE

illegal access interrupt enable for TIM8
USART1IE

illegal access interrupt enable for USART1
TIM15IE

illegal access interrupt enable for TIM5
TIM16IE

illegal access interrupt enable for TIM6
TIM17IE

illegal access interrupt enable for TIM7
SAI1IE

illegal access interrupt enable for SAI1

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32