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stm32 /stm32u5 /STM32U535 /GTZC1_TZIC /IER4

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Interpret as IER4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPDMA1IE)GPDMA1IE 0 (FLASH_REGIE)FLASH_REGIE 0 (FLASHIE)FLASHIE 0 (TZSC1IE)TZSC1IE 0 (TZIC1IE)TZIC1IE 0 (OCTOSPI1_MEMIE)OCTOSPI1_MEMIE 0 (BKPSRAMIE)BKPSRAMIE 0 (HSPI1_MEMIE)HSPI1_MEMIE 0 (SRAM1IE)SRAM1IE 0 (MPCBB1_REGIE)MPCBB1_REGIE 0 (SRAM2IE)SRAM2IE 0 (MPCBB2_REGIE)MPCBB2_REGIE 0 (SRAM5IE)SRAM5IE

Description

TZIC interrupt enable register 4

Fields

GPDMA1IE

illegal access interrupt enable for GPDMA1
FLASH_REGIE

illegal access interrupt enable for FLASH registers
FLASHIE

illegal access interrupt enable for FLASH memory
TZSC1IE

illegal access interrupt enable for GTZC1 TZSC registers
TZIC1IE

illegal access interrupt enable for GTZC1 TZIC registers
OCTOSPI1_MEMIE

illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank
BKPSRAMIE

illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank
HSPI1_MEMIE

illegal access interrupt enable for HSPI1 memory bank
SRAM1IE

illegal access interrupt enable for SRAM1
MPCBB1_REGIE

illegal access interrupt enable for MPCBB1 registers
SRAM2IE

illegal access interrupt enable for SRAM2
MPCBB2_REGIE

illegal access interrupt enable for MPCBB2 registers
SRAM5IE

illegal access interrupt enable for SRAM5

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32