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stm32 /stm32u5 /STM32U535 /GTZC1_TZIC /SR1

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Interpret as SR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2F)TIM2F 0 (TIM3F)TIM3F 0 (TIM4F)TIM4F 0 (TIM5F)TIM5F 0 (TIM6F)TIM6F 0 (TIM7F)TIM7F 0 (WWDGF)WWDGF 0 (IWDGF)IWDGF 0 (SPI2F)SPI2F 0 (USART3F)USART3F 0 (UART4F)UART4F 0 (UART5F)UART5F 0 (I2C1F)I2C1F 0 (I2C2F)I2C2F 0 (CRSF)CRSF 0 (I2C4F)I2C4F 0 (LPTIM2F)LPTIM2F 0 (FDCAN1F)FDCAN1F

Description

TZIC status register 1

Fields

TIM2F

illegal access flag for TIM2
TIM3F

illegal access flag for TIM3
TIM4F

illegal access flag for TIM4
TIM5F

illegal access flag for TIM5
TIM6F

illegal access flag for TIM6
TIM7F

illegal access flag for TIM7
WWDGF

illegal access flag for WWDG
IWDGF

illegal access flag for IWDG
SPI2F

illegal access flag for SPI2
USART3F

illegal access flag for USART3
UART4F

illegal access flag for UART4
UART5F

illegal access flag for UART5
I2C1F

illegal access flag for I2C1
I2C2F

illegal access flag for I2C2
CRSF

illegal access flag for CRS
I2C4F

illegal access flag for I2C4
LPTIM2F

illegal access flag for LPTIM2
FDCAN1F

illegal access flag for FDCAN1

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32