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stm32 /stm32u5 /STM32U535 /GTZC1_TZIC /SR3

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Interpret as SR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MDF1F)MDF1F 0 (CORDICF)CORDICF 0 (FMACF)FMACF 0 (CRCF)CRCF 0 (TSCF)TSCF 0 (ICACHE_REGF)ICACHE_REGF 0 (DCACHE1_REGF)DCACHE1_REGF 0 (ADC12F)ADC12F 0 (DCMIF)DCMIF 0 (HASHF)HASHF 0 (RNGF)RNGF 0 (SDMMC1F)SDMMC1F 0 (OCTOSPI1_REGF)OCTOSPI1_REGF 0 (RAMCFGF)RAMCFGF 0 (GPU2DF)GPU2DF 0 (HSPI1_REGF)HSPI1_REGF

Description

TZIC status register 3

Fields

MDF1F

illegal access flag for MDF1
CORDICF

illegal access flag for CORDIC
FMACF

illegal access flag for FMAC
CRCF

illegal access flag for CRC
TSCF

illegal access flag for TSC
ICACHE_REGF

illegal access flag for ICACHE registers
DCACHE1_REGF

illegal access flag for DCACHE registers
ADC12F

illegal access flag for ADC1 and ADC2
DCMIF

illegal access flag for DCMI
HASHF

illegal access flag for HASH
RNGF

illegal access flag for RNG
SDMMC1F

illegal access flag
OCTOSPI1_REGF

illegal access flag for OCTOSPI1 registers
RAMCFGF

illegal access flag for RAMCFG
GPU2DF

illegal access flag for GPU2D
HSPI1_REGF

illegal access flag for HSPI1 registers

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32