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stm32 /stm32u5 /STM32U535 /GTZC1_TZSC /TZSC_PRIVCFGR1

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Interpret as TZSC_PRIVCFGR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2PRIV)TIM2PRIV 0 (TIM3PRIV)TIM3PRIV 0 (TIM4PRIV)TIM4PRIV 0 (TIM5PRIV)TIM5PRIV 0 (TIM6PRIV)TIM6PRIV 0 (TIM7PRIV)TIM7PRIV 0 (WWDGPRIV)WWDGPRIV 0 (IWDGPRIV)IWDGPRIV 0 (SPI2PRIV)SPI2PRIV 0 (USART3PRIV)USART3PRIV 0 (UART4PRIV)UART4PRIV 0 (UART5PRIV)UART5PRIV 0 (I2C1PRIV)I2C1PRIV 0 (I2C2PRIV)I2C2PRIV 0 (CRSPRIV)CRSPRIV 0 (I2C4PRIV)I2C4PRIV 0 (LPTIM2PRIV)LPTIM2PRIV 0 (FDCAN1PRIV)FDCAN1PRIV

Description

TZSC privilege configuration register 1

Fields

TIM2PRIV

privileged access mode for TIM2
TIM3PRIV

privileged access mode for TIM3
TIM4PRIV

privileged access mode for TIM4
TIM5PRIV

privileged access mode for TIM5
TIM6PRIV

privileged access mode for TIM6
TIM7PRIV

privileged access mode for TIM7
WWDGPRIV

privileged access mode for WWDG
IWDGPRIV

privileged access mode for IWDG
SPI2PRIV

privileged access mode for SPI2
USART3PRIV

privileged access mode for USART3
UART4PRIV

privileged access mode for UART4
UART5PRIV

privileged access mode for UART5
I2C1PRIV

privileged access mode for I2C1
I2C2PRIV

privileged access mode for I2C2
CRSPRIV

privileged access mode for CRS
I2C4PRIV

privileged access mode for I2C4
LPTIM2PRIV

privileged access mode for LPTIM2
FDCAN1PRIV

privileged access mode for FDCAN1

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32