Regviz

stm32 /stm32u5 /STM32U535 /GTZC1_TZSC /TZSC_PRIVCFGR3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TZSC_PRIVCFGR3

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32u5/STM32U535/GTZC1_TZSC/TZSC_PRIVCFGR3#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MDF1PRIV)MDF1PRIV 0 (CORDICPRIV)CORDICPRIV 0 (FMACPRIV)FMACPRIV 0 (CRCPRIV)CRCPRIV 0 (TSCPRIV)TSCPRIV 0 (ICACHE_REGPRIV)ICACHE_REGPRIV 0 (DCACHE1_REGPRIV)DCACHE1_REGPRIV 0 (ADC1PRIV)ADC1PRIV 0 (DCMIPRIV)DCMIPRIV 0 (HASHPRIV)HASHPRIV 0 (RNGPRIV)RNGPRIV 0 (SDMMC1PRIV)SDMMC1PRIV 0 (OCTOSPI1_REGPRIV)OCTOSPI1_REGPRIV 0 (RAMCFGPRIV)RAMCFGPRIV 0 (GPU2DPRIV)GPU2DPRIV 0 (HSPI1_REGPRIV)HSPI1_REGPRIV

Description

TZSC privilege configuration register 3

Fields

MDF1PRIV

privileged access mode for MDF1
CORDICPRIV

privileged access mode for CORDIC
FMACPRIV

privileged access mode for FMAC
CRCPRIV

privileged access mode for CRC
TSCPRIV

privileged access mode for TSC
ICACHE_REGPRIV

privileged access mode for ICACHE registers
DCACHE1_REGPRIV

privileged access mode for DCACHE1 registers
ADC1PRIV

privileged access mode for ADC1
DCMIPRIV

privileged access mode for DCMI
HASHPRIV

privileged access mode for HASH
RNGPRIV

privileged access mode for RNG
SDMMC1PRIV

privileged access mode
OCTOSPI1_REGPRIV

privileged access mode for OCTOSPI1
RAMCFGPRIV

privileged access mode for RAMCFG
GPU2DPRIV

GPU2DPRIV
HSPI1_REGPRIV

HSPI1_REGPRIV

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32