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stm32 /stm32u5 /STM32U535 /GTZC1_TZSC /TZSC_SECCFGR2

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Interpret as TZSC_SECCFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1SEC)TIM1SEC 0 (SPI1SEC)SPI1SEC 0 (TIM8SEC)TIM8SEC 0 (USART1SEC)USART1SEC 0 (TIM15SEC)TIM15SEC 0 (TIM16SEC)TIM16SEC 0 (TIM17SEC)TIM17SEC 0 (SAI1SEC)SAI1SEC

Description

TZSC secure configuration register 2

Fields

TIM1SEC

secure access mode for TIM1
SPI1SEC

secure access mode for SPI1
TIM8SEC

secure access mode for TIM8
USART1SEC

secure access mode for USART1
TIM15SEC

secure access mode for TIM5
TIM16SEC

secure access mode for TIM6
TIM17SEC

secure access mode for TIM7
SAI1SEC

secure access mode for SAI1

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32