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stm32 /stm32u5 /STM32U535 /LPGPIO1 /LPGPIO_BSRR

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Interpret as LPGPIO_BSRR

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https://regviz.com/r/stm32/stm32u5/STM32U535/LPGPIO1/LPGPIO_BSRR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BS0)BS0 0 (BS1)BS1 0 (BS2)BS2 0 (BS3)BS3 0 (BS4)BS4 0 (BS5)BS5 0 (BS6)BS6 0 (BS7)BS7 0 (BS8)BS8 0 (BS9)BS9 0 (BS10)BS10 0 (BS11)BS11 0 (BS12)BS12 0 (BS13)BS13 0 (BS14)BS14 0 (BS15)BS15 0 (BR0)BR0 0 (BR1)BR1 0 (BR2)BR2 0 (BR3)BR3 0 (BR4)BR4 0 (BR5)BR5 0 (BR6)BR6 0 (BR7)BR7 0 (BR8)BR8 0 (BR9)BR9 0 (BR10)BR10 0 (BR11)BR11 0 (BR12)BR12 0 (BR13)BR13 0 (BR14)BR14 0 (BR15)BR15

Description

LPGPIO port bit set/reset register

Fields

BS0

BS0
BS1

BS1
BS2

BS2
BS3

BS3
BS4

BS4
BS5

BS5
BS6

BS6
BS7

BS7
BS8

BS8
BS9

BS9
BS10

BS10
BS11

BS11
BS12

BS12
BS13

BS13
BS14

BS14
BS15

BS15
BR0

BR0
BR1

BR1
BR2

BR2
BR3

BR3
BR4

BR4
BR5

BR5
BR6

BR6
BR7

BR7
BR8

BR8
BR9

BR9
BR10

BR10
BR11

BR11
BR12

BR12
BR13

BR13
BR14

BR14
BR15

BR15

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32