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stm32 /stm32u5 /STM32U545 /GTZC1_TZIC /SR4

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Interpret as SR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPDMA1F)GPDMA1F 0 (FLASH_REGF)FLASH_REGF 0 (FLASHF)FLASHF 0 (OTFDEC1F)OTFDEC1F 0 (TZSC1F)TZSC1F 0 (TZIC1F)TZIC1F 0 (OCTOSPI1_MEMF)OCTOSPI1_MEMF 0 (BKPSRAMF)BKPSRAMF 0 (HSPI1_MEMF)HSPI1_MEMF 0 (SRAM1F)SRAM1F 0 (MPCBB1_REGF)MPCBB1_REGF 0 (SRAM2F)SRAM2F 0 (MPCBB2_REGF)MPCBB2_REGF 0 (SRAM5F)SRAM5F

Description

TZIC status register 4

Fields

GPDMA1F

illegal access flag for GPDMA1
FLASH_REGF

illegal access flag for FLASH registers
FLASHF

illegal access flag for FLASH memory
OTFDEC1F

illegal access flag for OTFDEC1
TZSC1F

illegal access flag for GTZC1 TZSC registers
TZIC1F

illegal access flag for GTZC1 TZIC registers
OCTOSPI1_MEMF

illegal access flag for MPCWM1 (OCTOSPI1) memory bank
BKPSRAMF

illegal access flag for MPCWM3 (BKPSRAM) memory bank
HSPI1_MEMF

illegal access flag for HSPI1 memory bank
SRAM1F

illegal access flag for SRAM1
MPCBB1_REGF

illegal access flag for MPCBB1 registers
SRAM2F

illegal access flag for SRAM2
MPCBB2_REGF

illegal access flag for MPCBB2 registers
SRAM5F

illegal access flag for SRAM5

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32