status and interrupt register
| IRS | Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. |
| ILS | Interrupt high-level status The flag is set by hardware and reset by software. |
| IFS | Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. |
| IREN | Interrupt rising edge detection enable bit |
| ILEN | Interrupt high-level detection enable bit |
| IFEN | Interrupt falling edge detection enable bit |
| FEMPT | FIFO empty. Read-only bit that provides the status of the FIFO |