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stm32 /stm32u5 /STM32U575 /SYSCFG /CCCSR

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Interpret as CCCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN1)EN1 0 (CS1)CS1 0 (EN2)EN2 0 (CS2)CS2 0 (RDY1)RDY1 0 (RDY2)RDY2

Description

compensation cell control/status register

Fields

EN1

EN1
CS1

CS1
EN2

EN2
CS2

CS2
RDY1

RDY1
RDY2

RDY2

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32