stm32 /stm32wb /STM32WB10_CM4 /PWR /SR1

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Interpret as SR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CWUF1)CWUF1 0 (CWUF2)CWUF2 0 (CWUF3)CWUF3 0 (CWUF4)CWUF4 0 (CWUF5)CWUF5 0 (SDFBF)SDFBF 0 (BORHF)BORHF 0 (BLEWUF)BLEWUF 0 (WUF802)WUF802 0 (CRPEF)CRPEF 0 (BLEAF)BLEAF 0 (AF802)AF802 0 (C2HF)C2HF 0 (WUFI)WUFI

Description

Power status register 1

Fields

CWUF1

Wakeup flag 1

CWUF2

Wakeup flag 2

CWUF3

Wakeup flag 3

CWUF4

Wakeup flag 4

CWUF5

Wakeup flag 5

SDFBF

Step Down converter forced in Bypass interrupt flag

BORHF

BORH interrupt flag

BLEWUF

BLE wakeup interrupt flag

WUF802

802.15.4 wakeup interrupt flag

CRPEF

Enable critical radio phase end of activity interrupt flag

BLEAF

BLE end of activity interrupt flag

AF802

802.15.4 end of activity interrupt flag

C2HF

CPU2 Hold interrupt flag

WUFI

Internal Wakeup interrupt flag

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