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stm32 /stm32wb /STM32WB15_CM4 /PWR /SCR

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Interpret as SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CWUF1)CWUF1 0 (CWUF4)CWUF4 0 (CSMPSFBF)CSMPSFBF 0 (CBORHF)CBORHF 0 (CBLEWUF)CBLEWUF 0 (CCRPEF)CCRPEF 0 (CBLEAF)CBLEAF 0 (CC2HF)CC2HF

Description

Power status clear register

Fields

CWUF1

Clear wakeup flag 1
CWUF4

Clear wakeup flag 4
CSMPSFBF

Clear SMPS Step Down converter forced in Bypass interrupt flag
CBORHF

Clear BORH interrupt flag
CBLEWUF

Clear BLE wakeup interrupt flag
CCRPEF

Clear critical radio phase end of activity interrupt flag
CBLEAF

Clear BLE end of activity interrupt flag
CC2HF

Clear CPU2 Hold interrupt flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32