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stm32 /stm32wb /STM32WB15_CM4 /PWR /SR1

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Interpret as SR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WUF1)WUF1 0 (WUF4)WUF4 0 (SMPSFBF)SMPSFBF 0 (BORHF)BORHF 0 (BLEWUF)BLEWUF 0 (CRPEF)CRPEF 0 (BLEAF)BLEAF 0 (C2HF)C2HF 0 (WUFI)WUFI

Description

Power status register 1

Fields

WUF1

Wakeup flag 1
WUF4

Wakeup flag 4
SMPSFBF

Step Down converter forced in Bypass interrupt flag
BORHF

BORH interrupt flag
BLEWUF

BLE wakeup interrupt flag
CRPEF

Enable critical radio phase end of activity interrupt flag
BLEAF

BLE end of activity interrupt flag
C2HF

CPU2 Hold interrupt flag
WUFI

Internal Wakeup interrupt flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32