Regviz

stm32 /stm32wb /STM32WB35_CM4 /SAI1 /AFRCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as AFRCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB35_CM4/SAI1/AFRCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRL0FSALL0 (FSDEF)FSDEF 0 (FSPOL)FSPOL 0 (FSOFF)FSOFF

Description

Aframe configuration register

Fields

FRL

Frame length
FSALL

Frame synchronization active level length
FSDEF

Frame synchronization definition
FSPOL

Frame synchronization polarity
FSOFF

Frame synchronization offset

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32