stm32 /stm32wb /STM32WB50_CM4 /Flash /SRRVR

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Interpret as SRRVR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SBRV0SBRSA0 (BRSD)BRSD 0SNBRSA0 (NBRSD)NBRSD 0 (C2OPT)C2OPT

Description

Secure SRAM2 start address and cortex M0 reset vector register

Fields

SBRV

cortex M0 access control register

SBRSA

Secure backup SRAM2a start address

BRSD

backup SRAM2a security disable

SNBRSA

Secure non backup SRAM2a start address

NBRSD

non-backup SRAM2b security disable

C2OPT

CPU2 cortex M0 boot reset vector memory selection

Links

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