stm32 /stm32wb /STM32WB55_CM0P /SYSCFG_VREFBUF /SYSCFG_C2IMR2

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Interpret as SYSCFG_C2IMR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1_CH1_IM)DMA1_CH1_IM 0 (DMA1_CH2_IM)DMA1_CH2_IM 0 (DMA1_CH3_IM)DMA1_CH3_IM 0 (DMA1_CH4_IM)DMA1_CH4_IM 0 (DMA1_CH5_IM)DMA1_CH5_IM 0 (DMA1_CH6_IM)DMA1_CH6_IM 0 (DMA1_CH7_IM)DMA1_CH7_IM 0 (DMA2_CH1_IM)DMA2_CH1_IM 0 (DMA2_CH2_IM)DMA2_CH2_IM 0 (DMA2_CH3_IM)DMA2_CH3_IM 0 (DMA2_CH4_IM)DMA2_CH4_IM 0 (DMA2_CH5_IM)DMA2_CH5_IM 0 (DMA2_CH6_IM)DMA2_CH6_IM 0 (DMA2_CH7_IM)DMA2_CH7_IM 0 (DMAM_UX1_IM)DMAM_UX1_IM 0 (PVM1IM)PVM1IM 0 (PVM3IM)PVM3IM 0 (PVDIM)PVDIM 0 (TSCIM)TSCIM 0 (LCDIM)LCDIM

Description

CPU2 interrupt mask register 1

Fields

DMA1_CH1_IM

Peripheral DMA1 CH1 interrupt mask to CPU2

DMA1_CH2_IM

Peripheral DMA1 CH2 interrupt mask to CPU2

DMA1_CH3_IM

Peripheral DMA1 CH3 interrupt mask to CPU2

DMA1_CH4_IM

Peripheral DMA1 CH4 interrupt mask to CPU2

DMA1_CH5_IM

Peripheral DMA1 CH5 interrupt mask to CPU2

DMA1_CH6_IM

Peripheral DMA1 CH6 interrupt mask to CPU2

DMA1_CH7_IM

Peripheral DMA1 CH7 interrupt mask to CPU2

DMA2_CH1_IM

Peripheral DMA2 CH1 interrupt mask to CPU1

DMA2_CH2_IM

Peripheral DMA2 CH2 interrupt mask to CPU1

DMA2_CH3_IM

Peripheral DMA2 CH3 interrupt mask to CPU1

DMA2_CH4_IM

Peripheral DMA2 CH4 interrupt mask to CPU1

DMA2_CH5_IM

Peripheral DMA2 CH5 interrupt mask to CPU1

DMA2_CH6_IM

Peripheral DMA2 CH6 interrupt mask to CPU1

DMA2_CH7_IM

Peripheral DMA2 CH7 interrupt mask to CPU1

DMAM_UX1_IM

Peripheral DMAM UX1 interrupt mask to CPU1

PVM1IM

Peripheral PVM1IM interrupt mask to CPU1

PVM3IM

Peripheral PVM3IM interrupt mask to CPU1

PVDIM

Peripheral PVDIM interrupt mask to CPU1

TSCIM

Peripheral TSCIM interrupt mask to CPU1

LCDIM

Peripheral LCDIM interrupt mask to CPU1

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