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stm32 /stm32wb /STM32WB55_CM0P /SYSCFG_VREFBUF /SYSCFG_CFGR2

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Interpret as SYSCFG_CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLL)CLL 0 (SPL)SPL 0 (PVDL)PVDL 0 (ECCL)ECCL 0 (SPF)SPF

Description

CFGR2

Fields

CLL

Cortex-M4 LOCKUP (Hardfault) output enable bit
SPL

SRAM2 parity lock bit
PVDL

PVD lock enable bit
ECCL

ECC Lock
SPF

SRAM2 parity error flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32