Regviz

stm32 /stm32wb /STM32WB55_CM0P /SYSCFG_VREFBUF /SYSCFG_SIPCR

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Interpret as SYSCFG_SIPCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SAES1)SAES1 0 (SAES2)SAES2 0 (SPKA)SPKA 0 (SRNG)SRNG

Description

secure IP control register

Fields

SAES1

Enable AES1 KEY[7:0] security.
SAES2

Enable AES2 security.
SPKA

Enable PKA security
SRNG

Enable True RNG security

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32