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stm32 /stm32wb0 /STM32WB05 /FLASH_CTRL /CONFIG

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Interpret as CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (REMAP)REMAP 0 (DIS_GROUP_WRITE)DIS_GROUP_WRITE 0WAIT_STATE

Description

CONFIG register

Fields

REMAP

CPU access routing (it supersedes PREMAP configuration):

  • 0 : FLASH memory addressed
  • 1 : SRAM0 memory addressed
DIS_GROUP_WRITE

Burst write Control:

  • 0 : burst write allowed
  • 1 : burst write forbidden
WAIT_STATE

Add latency to flash read opeations:

  • 00 : no latency
  • 01 : 1 clock cycle latency
  • 10 : 2 clock cycles latency
  • 11 : 3 clock cycles latency

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32