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stm32 /stm32wb0 /STM32WB05 /GPIOA /AFRL

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Interpret as AFRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AFSEL00AFSEL10AFSEL20AFSEL3

Description

AFRL register

Fields

AFSEL0

y[3:0]: Alternate function selection for port A pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved
AFSEL1

y[3:0]: Alternate function selection for port A pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved
AFSEL2

y[3:0]: Alternate function selection for port A pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved
AFSEL3

y[3:0]: Alternate function selection for port A pin y (y = 0…7) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32