Regviz

stm32 /stm32wb0 /STM32WB05 /GPIOB /AFRH

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as AFRH

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb0/STM32WB05/GPIOB/AFRH#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0AFSEL120AFSEL130AFSEL140AFSEL15

Description

AFRH register

Fields

AFSEL12

y[3:0]: Alternate function selection for port B pin y (y = 8…15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved
AFSEL13

y[3:0]: Alternate function selection for port B pin y (y = 8…15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved
AFSEL14

y[3:0]: Alternate function selection for port B pin y (y = 8…15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved
AFSEL15

y[3:0]: Alternate function selection for port B pin y (y = 8…15) These bits are written by software to configure alternate function I/Os AFSELy selection: -0000: AF0 -0001: AF1 -0010: AF2 -0011: AF3 -0100: AF4 -0101: AF5 -0110: AF6 -0111: AF7 1xxx: Reserved

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32