Regviz

stm32 /stm32wb0 /STM32WB05 /PKA /PKA_SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PKA_SR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb0/STM32WB05/PKA/PKA_SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BUSY)BUSY 0 (PROCENDF)PROCENDF 0 (RAMERRF)RAMERRF 0 (ADDRERRF)ADDRERRF

Description

PKA_SR register

Fields

BUSY

PKA operation is in progress This bit is set to 1’ whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started.

  • 0: No operation is in progress (default)
  • 1: An operation is in progress Nota: if PKA is started with a wrong opcode the IP will be busy for a couple of cycles then it will abort automatically the operation and go back to ready (BUSY bit is set to 0’).
PROCENDF

PKA End of Operation flag

  • 0: Operation in progress
  • 1: PKA operation is completed. This flag is set when the BUSY bit is de-asserted.
RAMERRF

PKA RAM error flag

  • 0: No PKA RAM access error
  • 1: An AHB access to the PKA RAM occured while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress).
ADDRERRF

Address error flag

  • 0: No Address error
  • 1: Address access is out of range (unmapped address)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32