stm32 /stm32wb0 /STM32WB05 /PWRC /CR5

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Interpret as CR5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMPSLVL0 (B_0x0)SMPSBOMSEL 0 (B_0x0)SMPSFRDY 0 (B_0x0)SMPSLPOPEN 0 (B_0x0)SMPSFBYP 0 (B_0x0)NOSMPS 0 (B_0x0)SMPS_ENA_DCM 0 (B_0x0)CLKDETR_DISABLE 0 (B_0x0)SMPS_PRECH_CUR_SEL

SMPSFRDY=B_0x0, SMPSFBYP=B_0x0, SMPS_ENA_DCM=B_0x0, CLKDETR_DISABLE=B_0x0, SMPS_PRECH_CUR_SEL=B_0x0, NOSMPS=B_0x0, SMPSLPOPEN=B_0x0, SMPSBOMSEL=B_0x0

Description

CR5 register

Fields

SMPSLVL

SMPSLVL[3:0] SMPS Output Level Voltage Selection Select the SMPS output voltage with a granularity of 50mV. Default = ‘0100’ (1.4V) Vout = 1.2 + 0.05*SMPSOUT (V)

SMPSBOMSEL

SMPSBOMSEL: SMPS BOM Selection:

0 (B_0x0): BOM1

1 (B_0x1): BOM2 (default)

2 (B_0x2): BOM3

3 (B_0x3): n/a

SMPSFRDY

SMPSFB Force ready check When this bit is set, the SMPS FSM will consider the SMPS ready .

0 (B_0x0): no effect (by default)

1 (B_0x1): SMPS is considered READY

SMPSLPOPEN

SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed.

0 (B_0x0): in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO.

1 (B_0x1): in Low Power mode, SMPS is disabled, output is floating

SMPSFBYP

SMPSFB Force SMPS Regulator in bypass mode When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR.

0 (B_0x0): no effect (by default)

1 (B_0x1): SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1)

NOSMPS

NOSMPS: No SMPS Mode When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM.

0 (B_0x0): No effect, SMPS is enabled.

1 (B_0x1): SMPS is disabled;

SMPS_ENA_DCM

SMPS_ENA_DCM: enable discontinuous conduction mode

0 (B_0x0): disable

1 (B_0x1): enable

CLKDETR_DISABLE

CLKDETR_DISABLE: disable SMPS clock detection The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock.

0 (B_0x0): SMPS clock detection enabled (default)

1 (B_0x1): SMPS clock detection disabled

SMPS_PRECH_CUR_SEL

SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current

0 (B_0x0): 2.5mA

1 (B_0x1): 5mA

2 (B_0x2): 10mA

3 (B_0x3): 20mA (default)

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