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stm32 /stm32wb0 /STM32WB05 /PWRC /DBGR

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Interpret as DBGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DEEPSTOP2)DEEPSTOP2 0DIS_PRECH

Description

DBGR register

Fields

DEEPSTOP2

DEEPSTOP2: DEEPSTOP2 low power saving emulation enable. 0: normal DEEPSTOP will be applied 1: DEEPSTOP2 (debugger features not lost) will be applied instead of DEEPSTOP.
DIS_PRECH

DIS_PRECH[2:0]: disable precharge during deepstop (debug)

  • 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN)
  • 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1)
  • else: No effect (default 0x0)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32