stm32 /stm32wb0 /STM32WB05 /PWRC /EXTSRR

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Interpret as EXTSRR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DEEPSTOPF 0 (B_0x0)RFPHASEF

DEEPSTOPF=B_0x0, RFPHASEF=B_0x0

Description

EXTSRR register

Fields

DEEPSTOPF

DEEPSTOPF System DeepStop Flag This bit is set by hardware and cleared only by a POR reset or by writing ‘1’ in this bit field

0 (B_0x0): System has not been in DEEPSTOP mode

1 (B_0x1): System has been in DEEPSTOP mode

RFPHASEF

RFPHASEF RFPHASE Flag This bit is set by hardware after a Radio wake-up event (BLE activation); it is cleared either by software, writing ‘1’ in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP.

0 (B_0x0): RF IP does not require attention

1 (B_0x1): RF IP awake and requesting system attention

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