REGLPS=B_0x0, REGMS=B_0x0, SMPSRDY=B_0x0
SR2 register
| SMPSBYPR | SMPSBYPR: SMPS Force Bypass Control Replica This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. |
| SMPSENR | SMPSENR: SMPS Enable Control Replica This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. |
| SMPSRDY | SMPSRDY: SMPS Ready Status This bit provides the information whether SMPS is ready. 0 (B_0x0): SMPS regulator is not ready 1 (B_0x1): SMPS regulator is ready. |
| IOBOOTVAL2 | Bit3: PB15 input value on VDD33 latched at POR Bit2: PB14 input value on VDD33 latched at POR Bit1: PB13 input value on VDD33 latched at POR Bit0: PB12 input value on VDD33 latched at POR |
| REGLPS | REGLPS: Regulator Low Power Started This bit provides the information whether low power regulator is ready. 0 (B_0x0): LP regulator is not ready. 1 (B_0x1): LP regulator is ready. |
| REGMS | REGMS: Regulator Main LDO Started This bit provides the information whether main regulator is ready. 0 (B_0x0): Main regulator is not ready. 1 (B_0x1): Main regulator is ready. |
| PVDO | PVDO: Power Voltage Detector Output When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is lower than the selected PVD threshold (CR2.PVDLS) |
| IOBOOTVAL | Bit3: PA11 input value on VDD33 latched at POR Bit2: PA10 input value on VDD33 latched at POR Bit1: PA9 input value on VDD33 latched at POR Bit0: PA8 input value on VDD33 latched at POR |