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stm32 /stm32wb0 /STM32WB05 /RADIO_REG_REG /SYNTHCAL0_DIG_ENG

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Interpret as SYNTHCAL0_DIG_ENG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYNTHCAL_DEBUG_BUS_SEL 0SYNTH_IF_FREQ_CAL

Description

SYNTHCAL0_DIG_ENG register

Fields

SYNTHCAL_DEBUG_BUS_SEL

for Debug purpose
SYNTH_IF_FREQ_CAL

Define the frequency applied on the PLL during calibration phase

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32