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stm32 /stm32wb0 /STM32WB05 /RCC /AHBRSTR

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Interpret as AHBRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DMARST 0 (B_0x0)GPIOARST 0 (B_0x0)GPIOBRST 0 (B_0x0)CRCRST 0 (B_0x0)PKARST 0 (B_0x0)RNGRST

PKARST=B_0x0, GPIOBRST=B_0x0, DMARST=B_0x0, RNGRST=B_0x0, CRCRST=B_0x0, GPIOARST=B_0x0

Description

AHBRSTR register

Fields

DMARST

DMA and DMAMUX reset Set and reset by software.

0 (B_0x0): does not reset DMA

1 (B_0x1): resets DMA
GPIOARST

GPIOA reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
GPIOBRST

GPIOB reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
CRCRST

CRC reset Set and reset by software.

0 (B_0x0): does not reset CRC

1 (B_0x1): resets CRC
PKARST

PKA reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
RNGRST

RNG reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32