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stm32 /stm32wb0 /STM32WB05 /RCC /APB0RSTR

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Interpret as APB0RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1RST 0 (B_0x0)TIM16RST 0 (B_0x0)TIM17RST 0 (B_0x0)SYSCFGRST 0 (B_0x0)RTCRST 0 (B_0x0)WDRST

RTCRST=B_0x0, WDRST=B_0x0, SYSCFGRST=B_0x0, TIM17RST=B_0x0, TIM16RST=B_0x0, TIM1RST=B_0x0

Description

APB0RSTR register

Fields

TIM1RST

TIM1: Advanced Timer reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
TIM16RST

TIM16 reset

0 (B_0x0): TIM16 IP is not under reset

1 (B_0x1): TIM16 IP is under reset
TIM17RST

TIM17 reset

0 (B_0x0): TIM17 IP is not under reset

1 (B_0x1): TIM17 IP is under reset
SYSCFGRST

SYSTEM CONFIG reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
RTCRST

RTC reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets
WDRST

WATCHDOG reset Set and reset by software.

0 (B_0x0): does not reset

1 (B_0x1): resets

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32