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stm32 /stm32wb0 /STM32WB05 /RNG /RNG_SR

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Interpret as RNG_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RNGRDY)RNGRDY 0 (REVCLK)REVCLK 0 (FAULT)FAULT

Description

RNG_SR register

Fields

RNGRDY

New Random Value Ready.
REVCLK

RNGCLK Clock Reveal bit.
FAULT

Fault Reveal bit.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32