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stm32 /stm32wb0 /STM32WB05 /SYSTEM_CTRL /BLERXTX_IER

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Interpret as BLERXTX_IER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_IE)TX_IE 0 (RX_IE)RX_IE

Description

BLERXTX_IER register

Fields

TX_IE

TX_IE: interrupt enable on TX_SEQUENCE signal: 0: TX_SEQUENCE interrupt is disabled (default). 1: TX_SEQUENCE interrupt is enabled
RX_IE

RX_IE: interrupt enable on RX_SEQUENCE signal: 0: RX_SEQUENCE interrupt is disabled (default). 1: RX_SEQUENCE interrupt is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32