stm32 /stm32wb0 /STM32WB05 /TIM2 /CCER

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Interpret as CCER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CC1E)CC1E 0 (CC1P)CC1P 0 (B_0x0)CC1NP 0 (CC2E)CC2E 0 (CC2P)CC2P 0 (CC2NP)CC2NP 0 (CC3E)CC3E 0 (CC3P)CC3P 0 (CC3NP)CC3NP 0 (CC4E)CC4E 0 (CC4P)CC4P 0 (CC4NP)CC4NP

CC1NP=B_0x0

Description

CCER register

Fields

CC1E

CC1E: Capture/Compare 1 output enable

CC1 channel configured as output:

0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N

and CC1NE bits.

1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,

OSSR, OIS1, OIS1N and CC1NE bits.

CC1 channel configured as input:

This bit determines if a capture of the counter value can actually be done into the input

capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled

1: Capture enabled

CC1P

CC1P: Capture/Compare 1 output polarity

CC1 channel configured as output:

0: OC1 active high

1: OC1 active low

CC1 channel configured as input:

The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations…

00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or

trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger

operation in gated mode).

01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger

operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in

gated mode.

10: Reserved, do not use this configuration.

11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges

(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted

(trigger operation in gated mode).

Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK

bits in TIMx_BDTR register).

  1. On channels that have a complementary output, this bit is preloaded. If the CCPC bit

is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the

preloaded bit only when a Commutation event is generated.

CC1NP

CC1NP: Capture/Compare 1 Complementary output Polarity.

This field is not used in Blue51. Not available in IUM

Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK

bits in GPT_BDTR register) and CC1S=‘00’ (the channel is configured in output).

0 (B_0x0): OC1N active high.

1 (B_0x1): OC1N active low.

CC2E

CC2E: Capture/Compare 2 output enable

refer to CC1E description

CC2P

CC2P: Capture/Compare 2 output polarity

refer to CC1P description

CC2NP

CC2NP: Capture/Compare 2 Complementary output Polarity.

This field is not used in Blue51. Not available in IUM

refer to CC1NP description

CC3E

CC3E: Capture/Compare 3 output enable

refer to CC1E description

CC3P

CC3P: Capture/Compare 3 output polarity

refer to CC1P description

CC3NP

CC3NP: Capture/Compare 3 Complementary output Polarity.

This field is not used in Blue51. Not available in IUM

refer to CC1NP description

CC4E

CC4E: Capture/Compare 4 output enable

refer to CC1E description

CC4P

CC4P: Capture/Compare 4 output polarity

refer to CC1P description

CC4NP

CC4NP: Capture/Compare 4 Complementary output Polarity.

This field is not used in Blue51. Not available in IUM

refer to CC1NP description

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