MMS=B_0x0
CR2 register
| CCDS | CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs |
| MMS | MMS: Master Mode Selection. This field is not available in IUM as Timer2 is not connected to ant other timer for master/slave synchronization. These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follow : is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in GPT_SMCR register). can then be used as a prescaler for a slave timer. (even if it was already high), as soon as a capture or a compare match occured. (TRGO). 0 (B_0x0): Reset - the UG bit from the GPT_EGR register is used as trigger output (TRGO). If the reset 1 (B_0x1): Enable - the Counter Enable signal cnt_en is used as trigger output (TRGO). It is useful to 2 (B_0x2): Update - The update event is selected as trigger output (TRGO). For instance a master timer 3 (B_0x3): Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set 4 (B_0x4): Compare - OC1REF signal is used as trigger output (TRGO). 5 (B_0x5): Compare - OC2REF signal is used as trigger output (TRGO). 6 (B_0x6): Compare - OC3REF signal is used as trigger output (TRGO). 7 (B_0x7): Compare - OC4REF signal is used as trigger output (TRGO). |
| TI1S | TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) |