DMAR register
| DMAB | DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIM2_CR1 address) + (DBA + DMA index) x 4 where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM2_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). |