I2C2_ICR register
| ADDRCF | Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register. |
| NACKCF | Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register. |
| STOPCF | Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. |
| BERRCF | Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. |
| ARLOCF | Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. |
| OVRCF | Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register. |
| PECCF | PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation. |
| TIMOUTCF | Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation. |
| ALERTCF | Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section 22.3: I2C implementation. |