| RXNE | Receive buffer not empty
- 0: Rx buffer empty
- 1: Rx buffer not empty
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| TXE | Transmit buffer empty
- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer).
- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer).
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| CHSIDE | Channel side
- 0: Channel Left has to be transmitted or has been received
- 1: Channel Right has to be transmitted or has been received
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| UDR | Underrun flag
- 0: No underrun occurred
- 1: Underrun occurred
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| CRCERR | CRC error flag
- 0: CRC value received matches the SPIx_RXCRCR value
- 1: CRC value received does not match the SPIx_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
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| MODF | Mode fault
- 0: No mode fault occurred
- 1: Mode fault occurred
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| OVR | Overrun flag
- 0: No overrun occurred
- 1: Overrun occurred
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| BSY | Busy flag
- 0: SPI (or I2S) not busy
- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
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| FRE | Frame format error
This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags.
This flag is set by hardware and reset when SPIx_SR is read by software.
- 0: No frame format error
- 1: A frame format error occurred
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| FRLVL | FIFO reception level
These bits are set and cleared by hardware.
- 00: FIFO empty
- 01: 1/4 FIFO
- 10: 1/2 FIFO
- 11: FIFO full
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| FTLVL | FIFO Transmission Level
These bits are set and cleared by hardware.
- 00: FIFO empty
- 01: 1/4 FIFO
- 10: 1/2 FIFO
- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)
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