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stm32 /stm32wb0 /STM32WB06 /TIM1 /CCR5

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Interpret as CCR5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CCR50 (GC5C1)GC5C1 0 (GC5C2)GC5C2 0 (GC5C3)GC5C3

Description

CCR5 register

Fields

CCR5

Capture/compare 5 value
GC5C1

Group channel 5 and channel 1 distortion on channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: It is also possible to apply this distortion on combined PWM signals.
GC5C2

Group channel 5 and channel 2 distortion on channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: It is also possible to apply this distortion on combined PWM signals.
GC5C3

Group channel 5 and channel 3 distortion on channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: It is also possible to apply this distortion on combined PWM signals.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32