ADC configuration register
| CONT | regular sequence runs continuously when ADC mode is enabled |
| SEQUENCE | enable the sequence mode (active by default) |
| SEQ_LEN | number of conversions in a regular sequence |
| SMPS_SYNCHRO_ENA | synchronize the ADC start conversion with a pulse generated by the |
| OP_MODE | ADC mode selection (= data path selection) |
| SAMPLE_RATE | conversion rate of ADC |
| DMA_DS_ENA | enable DMA mode for Down Sampler data path |
| DMA_DF_ENA | enable DMA mode for Decimation Filter data path |
| OVR_DS_CFG | Down Sampler overrun configuration |
| OVR_DF_CFG | decimation overrun configuration |
| BIT_INVERT_SN | invert bit to bit the ADC data output when a single |
| BIT_INVERT_DIFF | invert bit to bit the ADC data output when a differential |
| ADC_CONT_1V2 | select the input sampling method |
| VBIAS_PRECH_FORCE | possibility to keep the VBIAS_PRECH enabled to deactivate the filter |