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stm32 /stm32wb0 /STM32WB07 /ADC /DF_CONF

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Interpret as DF_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DF_CIC_DEC_FACTOR 0 (DF_CIC_DHF)DF_CIC_DHF 0 (DF_ITP1P2)DF_ITP1P2 0 (DF_I_U2S)DF_I_U2S 0 (DF_O_S2U)DF_O_S2U 0PDM_RATE 0 (DF_MICROL_RN)DF_MICROL_RN 0 (DF_HPF_EN)DF_HPF_EN 0 (DF_HALF_D_EN)DF_HALF_D_EN

Description

Decimation filter configuration register

Fields

DF_CIC_DEC_FACTOR
DF_CIC_DHF

CIC filter decimator half factor
DF_ITP1P2

1.2 fractional interpolator enable
DF_I_U2S

select signed/unsigned format for input
DF_O_S2U

select signed/unsigned format for data output
PDM_RATE

select the PDM clock rate.
DF_MICROL_RN

left/right channel selection on digital microphone
DF_HPF_EN

high pass filter enable.
DF_HALF_D_EN

half dynamic enable.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32