CCOPRE=B_0x0, IOBOOSTEN=B_0x0, SPI3I2SCLKSEL=B_0x0, LCOSEL=B_0x0, SMPSDIV=B_0x0, MCOSEL=B_0x0, STOPHSI=B_0x0, HSESEL=B_0x0, SMPSINV=B_0x0, CLKSLOWSEL=B_0x0
CFGR register
| SMPSINV | bit to control inversion of the SMPS clock 0 (B_0x0): SMPS clock not inverted (default value) 1 (B_0x1): SMPS clock inverted (for debug) |
| HSESEL | Clock source selection request: 0 (B_0x0): HSI clock source is requested (default) 1 (B_0x1): HSE clock source is requested |
| STOPHSI | Stop HSI clock source request 0 (B_0x0): HSI is enabled (default) 1 (B_0x1): disable HSI is requested |
| CLKSYSDIV | CLKSYSDIV: system clock divided factor from HSI_64M. |
| SMPSDIV | SMPS clock prescaling factor to generate 4MHz or 8MHz 0 (B_0x0): div 2 when ANADIV=2 or 4 (default ) 1 (B_0x1): div 4 when ANADIV=1 or 2 |
| CLKSLOWSEL | slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn 0 (B_0x0): LSILMPU oscillator clock (default) 1 (B_0x1): LSE oscillator clock used as slow clock 2 (B_0x2): LSI oscillator clock used as slow clock 3 (B_0x3): HSI_64M divided by 2048 used as slow clock |
| IOBOOSTEN | IO BOOSTER enable Set and reset by software. 0 (B_0x0): does not enable IO BOOSTER 1 (B_0x1): enable IO BOOSTER |
| SPI3I2SCLKSEL | Selection of I2S1 clock: 1x:64MHz peripheral clock 0 (B_0x0): 16MHz peripheral clock (default) 1 (B_0x1): 32MHz peripheral clock |
| SPI2I2SCLKSEL | Selection of I2S clock: 1x:64MHz peripheral clock |
| LCOSEL | Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn 0 (B_0x0): LCO output disabled, no clock on LCO 1 (B_0x1): internal 32 KHz (LSI_LPMU) oscillator clock selected 2 (B_0x2): internal 32 KHz (LSI) oscillator clock selected 3 (B_0x3): external 32 KHz (LSE) oscillator clock selected |
| MCOSEL | Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. 0 (B_0x0): MCO output disabled, no clock on MCO 1 (B_0x1): system clock selected 2 (B_0x2): na 3 (B_0x3): internal RC 64 MHz (HSI) oscillator clock selected 4 (B_0x4): external oscillator (HSE) clock selected 5 (B_0x5): internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected 6 (B_0x6): SMPS clock selected 7 (B_0x7): AUX ADC ANA clock selected |
| CCOPRE | Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used 0 (B_0x0): CCO clock is divided by 1 1 (B_0x1): CCO clock is divided by 2 2 (B_0x2): CCO clock is divided by 4 3 (B_0x3): CCO clock is divided by 8 4 (B_0x4): CCO clock is divided by 16 |