LSIRDYIF=B_0x0, HSIPLLRDYIF=B_0x0, HSIRDYIF=B_0x0, LSERDYIF=B_0x0, HSERDYIF=B_0x0
CIFR register
| LSIRDYIF | LSI Ready Interrupt flag Set by hardware when LSI clock becomes stable. 0 (B_0x0): No clock ready interrupt caused by the internal RC 32 KHz oscillator 1 (B_0x1): Clock ready interrupt caused by the internal RC 32 kHz oscillator |
| LSERDYIF | LSE Ready Interrupt Flag. Set by hardware when LSE clock becomes stable. 0 (B_0x0): No clock ready interrupt caused by the LSE oscillator 1 (B_0x1): Clock ready interrupt caused by the LSE oscillator |
| HSIRDYIF | HSI Ready Interrupt Flag. Set by hardware when HSI becomes stable. 0 (B_0x0): No clock ready interrupt caused by the HSI oscillator 1 (B_0x1): Clock ready interrupt caused by the HSI oscillator |
| HSERDYIF | HSE Ready Interrupt Flag. Set by hardware when HSE becomes stable. 0 (B_0x0): No clock ready interrupt caused by the HSE oscillator 1 (B_0x1): Clock ready interrupt caused by the HSE oscillator |
| HSIPLLRDYIF | HSI PLL Ready Interrupt Flag. Set by hardware when HSI PLL 64MHz becomes stable. 0 (B_0x0): No clock ready interrupt caused by the HSI PLL64 MHz oscillator 1 (B_0x1): Clock ready interrupt caused by the HSI PLL64 MHz oscillator |
| HSIPLLUNLOCKDETIF | HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. |
| RTCRSTIF | RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock |
| WDGRSTIF | WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock |