TST_CLK=B_0x0, RNG_DIS=B_0x0
RNG_CR register
| RNG_DIS | This bit enables or disables the random number generator. 0: RNG is enabled (default) 1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block. 0 (B_0x0): The RNG core is enabled 1 (B_0x1): The RNG core is disabled |
| TST_CLK | Reset reveal clock error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. 0 (B_0x0): no reset 1 (B_0x1): reset revclk flag |