CCMR2 register
| CC3S | CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). |
| OC3FE | OC3FE: Output compare 3 fast enable |
| OC3PE | OC3PE: Output compare 3 preload enable |
| OC3M_2_0 | OC3M: Output compare 3 mode |
| OC3CE | OC3CE: Output compare 3 clear enable |
| CC4S | CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). |
| OC4FE | OC4FE: Output Compare 4 fast enable |
| OC4PE | OC4PE: Output Compare 4 preload enable |
| OC4M_2_0 | OC4M[2:0]: Output Compare 4 mode |
| OC4CE | OC4CE: Output Compare 4 clear enable |
| OC3M_3 | OC3M[3]: Output Compare 3 mode (bit 3) |
| OC4M_3 | OC4M[3]: Output Compare 4 mode (bit 3) |