Regviz

stm32 /stm32wb0 /STM32WB07 /TIM1 /CCMR3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CCMR3

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb0/STM32WB06/TIM1/CCMR3#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OC5FE)OC5FE 0 (OC5PE)OC5PE 0OC5M_2_0 0 (OC5CE)OC5CE 0 (OC6FE)OC6FE 0 (OC6PE)OC6PE 0OC6M_2_0 0 (OC6CE)OC6CE 0 (OC5M_3)OC5M_3 0 (OC6M_3)OC6M_3

Description

CCMR3 register

Fields

OC5FE

Output compare 5 fast enable
OC5PE

Output compare 5 preload enable.
OC5M_2_0

Output compare 5 mode.
OC5CE

Output compare 5 clear enable.
OC6FE

Output compare 6 fast enable.
OC6PE

Output compare 6 preload enable.
OC6M_2_0

Output compare 6 mode.
OC6CE

Output compare 6 clear enable.
OC5M_3

Output compare 5 mode - bit 3.
OC6M_3

Output compare 6 mode - bit 3.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32