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stm32 /stm32wb0 /STM32WB07 /TIM1 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCPC)CCPC 0 (CCUS)CCUS 0 (TI1S)TI1S 0 (OIS1)OIS1 0 (OIS1N)OIS1N 0 (OIS2)OIS2 0 (OIS2N)OIS2N 0 (OIS3)OIS3 0 (OIS3N)OIS3N 0 (OIS4)OIS4 0 (OIS5)OIS5 0 (OIS6)OIS6

Description

CR2 register

Fields

CCPC

Capture/compare preloaded control.
CCUS

Capture/compare control update selection.
TI1S

TI1S: TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input.

1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
OIS1

Output idle state 1 (OC1 output).
OIS1N

Output idle state 1 (OC1N output).
OIS2

Output idle state 2 (OC2 output). Refer to OIS1 bit.
OIS2N

Output idle state 2 (OC2N output). Refer to OIS1N bit.
OIS3

Output idle state 3 (OC3 output). Refer to OIS1 bit.
OIS3N

Output idle state 3 (OC3N output). Refer to OIS1N bit.
OIS4

Output idle state 4 (OC4 output). Refer to OIS1 bit.
OIS5

Output idle state 5 (OC5 output). Refer to OIS1 bit.
OIS6

Output idle state 6 (OC6 output). Refer to OIS1 bit.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32