STATUS=B_0x0, EOFSEQ_IE=B_0x0, CLKSYSDIV_REQ=B_0x0, EOFSEQ_IRQ=B_0x0, REQUEST=B_0x0
CSCMDR register
| REQUEST | Request for system clock switching Cleared by hardware when system clock frequency switch is done 0 (B_0x0): To cancel an ongiong request still possible until IRQ assertion 1 (B_0x1): To update the system clock frequency |
| CLKSYSDIV_REQ | system clock dividing factor from HSI_64M requested Note: behavior depends on BLEEN in APB2ENR register 0 (B_0x0): div 1 (sys clock 64M) 1 (B_0x1): div 2 (sys clock 32M) 2 (B_0x2): div 4 (sys clock 16M) 3 (B_0x3): div 8 (sys clock 8M) 4 (B_0x4): div 16 (sys clock 4M) 5 (B_0x5): div 32 (sys clock 2M) 6 (B_0x6): div 64 (sys clock 1M) |
| STATUS | Status of clock switch sequence 0 (B_0x0): IDLE no switch requested 1 (B_0x1): ONGOING clock frequency switch is ongoing 2 (B_0x2): DONE clock frequency switch done |
| EOFSEQ_IE | End of sequence Interrupt Enable. Set and reset by software to enable/disable interrupt caused by the clock system switch. 0 (B_0x0): End of sequence interrupt disabled 1 (B_0x1): End of sequence interrupt enabled |
| EOFSEQ_IRQ | End of Sequence flag Set by hardware when clock system swtich is ended 0 (B_0x0): No end of sequence event occured 1 (B_0x1): End of sequece event occured |