stm32 /stm32wb0 /STM32WB09 /TIM2 /CCMR1

CC1S: Capture/Compare 1 Selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

1x: Reserved

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

OC1FE: Output Compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is

5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC

is set to the compare level independently of the result of the comparison. Delay to sample

the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if

the channel is configured in PWM1 or PWM2 mode.

OC1PE: Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the

new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload

register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed

(LOCK bits in TIMx_BDTR register) and CC1S=‘00’ (the channel is configured in

output).

Note: 2: The PWM mode can be used without validating the preload register only in one

pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

OC1M: Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and

OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends

on CC1P and CC1NP bits.

0000: Frozen The comparison between the output compare register TIMx_CCR1 and the

counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing

base).

0001: Set channel 1 to active level on match. OC1REF signal is forced high when the

counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the

counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

0011: Toggle OC1REF toggles when TIMx_CNT=TIMx_CCR1.

0100: Force inactive level OC1REF is forced low.

0101: Force active level OC1REF is forced high.

0110: PWM mode 1 In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1

else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as

TIMx_CNT>TIMx_CCR1 else active (OC1REF=‘1’).

0111: PWM mode 2 In upcounting, channel 1 is inactive as long as

TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as

TIMx_CNT>TIMx_CCR1 else inactive.

1000: Retrigerrable OPM mode 1 In up-counting mode, the channel is active until a trigger

event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1

and the channels becomes active again at the next update. In down-counting mode, the

channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is

performed as in PWM mode 1 and the channels becomes inactive again at the next update.

1001: Retrigerrable OPM mode 2 In up-counting mode, the channel is inactive until a

trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM

mode 2 and the channels becomes inactive again at the next update. In down-counting

mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a

comparison is performed as in PWM mode 1 and the channels becomes active again at the

next update.

1010: Reserved

1011: Reserved

1100: Combined PWM mode 1 OC1REF has the same behavior as in PWM mode 1.

OC1REFC is the logical OR between OC1REF and OC2REF.

1101: Combined PWM mode 2 OC1REF has the same behavior as in PWM mode 2.

OC1REFC is the logical AND between OC1REF and OC2REF

1110: Asymmetric PWM mode 1 OC1REF has the same behavior as in PWM mode 1.

OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting

down.

1111: Asymmetric PWM mode 2 OC1REF has the same behavior as in PWM mode 2.

OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting

down.

Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed

(LOCK bits in TIMx_BDTR register) and CC1S=‘00’ (the channel is configured in

output).

Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison

changes or when the output compare mode switches from ‘frozen’ mode to ‘PWM’

mode.

OC1CE: Output Compare 1 Clear Enable

0: OC1Ref is not affected by the ETRF Input

1: OC1Ref is cleared as soon as a High level is detected on ETRF input

CC2S[1:0]: Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input. .

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if

an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

OC2FE: Output Compare 2 fast enable

OC2PE: Output Compare 2 preload enable

OC2M[2:0]: Output Compare 2 mode

OC2CE: Output Compare 2 clear enable

OC1M[3]: Output Compare 1 mode (bit 3)

OC2M[3]: Output Compare 2 mode (bit 3)